About Me

I received an bachlors of engineering degree in electronics engineering from Pune University, India and the Ph.D. in electrical engineering from the Indian Institute of Technology, Bombay (popularly known as IIT Bombay). I worked at GDA Technologies Limited, India before joining my Ph.D. in 2009. After completing Ph.D. I have joined as a faculty at the Department of Electrical Engineering, Indian Institute of Technology, Ropar (IIT Ropar), IN in 2016, where I currently as an assistant Professor. My research interests are in analog integrated circuits and the applications they enable in sensing, and power management.

Contact Details

Dr. Vinayak Hande
Office no. 350, IIT Ropar,
Rupnagar, Punjab 140 001,
India

(01881) 24-2110
anyone@website.com

Teaching

Fall 2016 : EEL 487 - Analog IC Design (Theory course for 3 yr/4 yr UG and PG)

Fall 2016 : EEP 205 - Digital Electronics (Lab course for 2 yr UG)

Spring 2017 : EEL 204 - Analog Electronics (Theory course for 2 yr UG)

Spring 2017 : EEP 204 - Analog Electronics (Lab course for 2 yr UG)

Fall 2017 : EEL 487 - Analog IC Design (Theory course for 3 yr/4 yr UG and PG)

Fall 2017 : EEP 205 - Digital Electronics (Lab course for 2 yr UG)

Spring 2018 : EEL 204 - Analog Electronics (Theory course for 2 yr UG)

Spring 2018 : EEP 204 - Analog Electronics (Lab course for 2 yr UG)

Work

Circuit Techniques for Low Power Voltage Reference Generator

Proposed different architectures of the voltage reference circuit to solve the problems of conventional bandgap based and non-bandgap (only CMOS) based reference circuits, such as, accuracy, area, power consumption, PSNA.

Design of energy efficient SA ADC.

Developing new switching techniques for DAC used in SA ADC. Such techniques reduce the energy consumption and helps to design low power data converters.

Design and Optimization of High Precision CMOS Voltage Reference Using Taguchi Orthogonal Array Technique

Taguchi method involves reducing the variation in a process through systematic design of experiments. The optimized voltage reference circuit show 20 % improvement over reported architecture for ≈ 50 % lesser supply voltage.

Indirect compensation method for two stage operational amplifier

Novel split-gm method is presented to introduce a LHP zero. 3-dB BW of two stage op-amp is increased by 3 times for comparable phase margin.

Skills

Students are completely skilled with designing of analog ICs in IIT Ropar.

  • Teaching
  • Designing
  • Simulating
  • Fabricating in Silicon
  • Testing
  • Publication

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Client Testimonials

  • Art of solving problem that cannot be formulated before they have been solved. The shaping of the question is a part of the answer.

    Peit Hein
  • Design is intermediary between information and understanding.

    Hans Hoffman

Get In Touch.

Interested in working together? Fill out the form with some info about you and I will get back to you as soon as I can. Please allow couple of days for me to respond

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