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  • Sahibia Kaur, Research Scholar, under the supervision of Devarshi Mrinal Das,Mahendra Sakare, Dr.Sahibia Kaur joined the Forschungszentrum Jülich, Germany, as a Researcher in Neuromorphic .
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Mahendra Sakare

Assistant Professor
Office location: Room no. 315, 2nd floor, J C Bose block. Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar, Punjab - 140001, India
mahendra@iitrpr.ac.in
+91-1881-23-2214
Google Scholar Profile


Introduction

Dr. Mahendra Sakare has been a faculty member in the Department of Electrical Engineering at the Indian Institute of Technology (IIT) Ropar since 2018. He completed his PhD from IIT Bombay in the year 2017. He was also a faculty member of the Department of Electronics and Communication Engineering at NIT Surathkal and NIT Rourkela for a very short period of time before joining IIT Ropar.

Research Highlights

3

Journal Publications

7

Conference Publications

5

Research Projects

14

Patents

1

Awards & Honours

Qualifications
  1. Doctor of Philosophy (Ph.D.) Electrical Engineering Indian Institute of Technology Bombay Mumbai India
  2. Master of Technology (M. Tech.) Microelectronics and VLSI SGSITS Indore Madhya Pradesh India
  3. Bachelor of Engineering (B. E.) Electrical Engineering RGPV Bhopal Madhya Pradesh India.
Research Interests
  • CMOS analog integrated circuit design.
  • High speed CMOS integrated circuits and systems.
  • ASIC for High frequency applications.
Brief Research Profile

A broad area of his research is analog circuit design. More specifically, his research focuses on high-speed integrated circuit design for chip-to-chip communication.

  1. 1. Puneet Singh, Mayank, Vinayak Hande, and Mahendra Sakare, "An active inductor employed CML latch for high speed integrated circuits", Analog Integrated Circuits and Signal Processing, 114,  pages 277–286, 2022
  2. 2. Mahendra Sakare, "A Power and Area Efficient Architecture of a PRBS Generator With Multiple Output", Transactions on circuits and systems - part II: Express briefs, 64,  pp. 927-931, 2017
  3. 3. Mahendra Sakare, Pavan Kumar Sadhu and Shalabh Gupta, "Bandwidth enhancement of flip-flops using feedback for high-speed integrated circuits,", Transactions on Circuits and Systems II: Express Briefs, 63,  pp. 768-772, 2016

  • 1. Patent, "A symmetrical differential exclusive XOR gate" ISBN: published by - Indian Year: 2021 authors- Mahendra Sakare, Puneet Singh, and Mayank Kumar Singh
  • 2. Patent, "A Circuit facilitating optimisation of data frequency and power consumption and a method thereof" ISBN: published by - Indian Year: 2023 authors- Mahendra Sakare, Puneet Singh, and Mayank Kumar Singh
  • 3. Patent, "An equalizer and method of operation thereof" ISBN: published by - Indian Year: 2023 authors- Mahendra Sakare, Puneet Singh, Rahul Walia, and Raja Sekhar Nagulapalli
  • 4. Patent, "A linearity improved equalizers for short-channel communication links" ISBN: published by - Indian Year: 2024 authors- Mahendra Sakare, Puneet Singh, Rahul Walia, and Raja Sekhar Nagulapalli
  • 5. Patent, "A phase frequency detector and its method of operation thereof" ISBN: published by - Indian Year: 8th March 2024 authors- Mayank Kumar Singh, Hirensh Mehra, Rajasekhar Nagulapalli, and Mahendra Sakare
  • 6. Patent, "An electronic device and fabrication method thereof" ISBN: published by - Indian Year: 30th Nov 2023 authors- Mayank Kumar Singh, Upendra Chichhula, Rajasekhar Nagulapalli, and Mahendra Sakare
  • 7. Patent, "Bandgap reference (BGR) circuit for generating BGR voltage and a method\nthereof" ISBN: published by - US Patent Year: 27th Sept 2023 authors- Mayank Kumar Singh, Rajasekhar Nagulapalli, and Mahendra Sakare
  • 8. Patent, "A constant slope circuit for high-speed applications," ISBN: published by - Indian Year: 11th Feb 2022 authors- Mayank Kumar Singh, Puneet Singh, and Mahendra Sakare
  • 9. Patent, "A Single-Tank Quadrature Voltage Controlled Oscillator (QVCO) and method of Operation thereof" ISBN: published by - Indian Year: 12th Feb 2024 authors- Mayank Kumar Singh, Hirensh Mehra, Rajasekhar Nagulapalli, and Mahendra Sakare
  • 10. Patent, "A Resistor Assisted Supply Sensitivity Improved Ring Oscillator for Wireline and Wireless Applications" ISBN: published by - Indian Year: 25th Sept 2024 authors- Mayank Kumar Singh, Hirensh Mehra, Rajasekhar Nagulapalli, and Mahendra Sakare
  • 11. Patent, "AN IMPROVED ULTRA-LOW MISMATCH CHARGE PUMP CIRCUIT FOR SERIALIZER/DESERIALIZER (SERDES) SYSTEMS" ISBN: published by - Indian Year: 24/06/2024 authors- Hirensh Mehra, Mayank Kumar Singh, Puneet Singh, Mahendra Sakare, and Rajasekhar Nagulapalli
  • 12. Patent, "A Noise and Mismatch Improved Resistor-based Charge Pump for Serializer/Deserializer (SerDes) applications." ISBN: published by - Indian Year: - authors- Hirensh Mehra, Mayank Kumar Singh, Mahendra Sakare, and Rajasekhar Nagulapalli
  • 13. Patent, "A dual tank technique to improve the Phase Noise of the VCO" ISBN: published by - Indian Year: 25th April 2024 authors- Zahid Rashid Sheikh, Rajasekhar Nagulapalli, Hitesh Shrimali,Mahendra Sakare
  • 14. Patent, "12GHz Quadrature VCO using the current reusing technique" ISBN: published by - Indian Year: 2nd july 2024 authors- Zahid Rashid Sheikh, Taranveer Kaur, Rajasekhar Nagulapalli, Hitesh Shrimali,Mahendra Sakare

S. No. Title Funding Agency Role Start Year - End Year Amount (In Lacs) Details
1 6 Gb/s transciever design\r\nfor chip to chip communication ISIRD, IIT Ropar PI 2019 - 2019 7.000
2 Support for lab equipment (RF source generator) ISIRD, IIT Ropar PI 2021 - 2021 107.000
3 Low power programmable multiple uncorrelated output PRBS generator integrated circuit CRG, SERB, GoI PI 2022 - 2025 26.000
4 ASIC and Package Design of Ultra Small Atomic Clock SMDP-C2S of MeitY CO-PI 2023 - 2028 285.000

S. No. Title Funding Agency Start Year - End Year Amount (In Lacs) Details
1 Audit of ClllTs of I. K. Gujral Punjab Technical University, Kapurthala (Hub) and Jabbowal, Sultanpur Lodhi (Spoke) I. K. Gujral Punjab Technical University, Punjab. 2022 - 2022 11.800

Code Title L-T-P-S-C Type Degree Year Semester
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2024 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2024 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2024 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2024 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2023 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2023 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2023 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2023 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2023 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2023 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2023 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2023 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2022 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2022 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2022 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2022 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2021 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2021 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2021 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2021 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2020 Semester I
EE301 Analog circuits 3-1-0-5-3 core B.tech. 2020 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2020 Semester I
EE302 Analog Circuits Lab 0-0-3-1.5-1.5 core B.tech. 2020 Semester I

  • 1. DC member of Sunil Pathania (2017EEZ0005), Saurabh Jaiswal (2019csz0009), Prabuddha sinha (2019csz0008),
  • 2. I am one of the faculties who proposed MTech (Microelectronics and VLSI design) at IIT Ropar.
  • 3. Developed Electrical hardware part for Tinkering lab, which was conducted for the first time after revised UG curriculum. Since then, the same equipment is in use.
  • 4. Faculty advisor of the 2020 EE batch, IIT Ropar.
  • 5. Departmental representative of Academic Committee for Continuing Education and Outreach Activities (ACCEOA) at IIT Ropar.
  • 6. Contributed as web chair in organizing committee in International Conference on Advances in VLSI and Embedded Systems (AVES) 2019 conducted by SVNIT Surat India.
  • 7. Departmental member for PMRF Shortlisting Policy and shortlisting for year 2021 and 2022.
  • 8. Departmental member of Committee for organizing "Dynamic Website Challenge" for year 2023.
  • 9. Served as a reviewer in the 4th EAI International Conference on Cognitive Computing and Cyber-Physical Systems 2023.
  • 10. Electrical Engineering department representative for Visvesvaraya PhD scheme from July 2023.
  • 11. Faculty advisor of Jammu & Kasmir cell at IIT Ropar w.e.f. 14 May 2024.
  • 12. Faculty member of Anti Ragging Squad (ARS) 2024 of IIT Ropar.
  • 13. Member of advisory committee for construction and planning (ACCP) 2024 of IIT Ropar.

Awards And Honours

1. Received International travel support (ITS) - DST (File no. SB/ITS/0779/2014-15) in 2014.

Academic Visits

1. VLSI Physical Design Techniques

Delivered two expert talks/lectures on online short term course on “VLSI Physical Design Techniques” conducted by National Institute of Technical Technical Teachers Training & Research, Chandigarh, Punjab, India held on 19 June 2020.

2. Mixed Signal and Radio Frequency VLSI Design

Delivered two expert talks/lectures in AICTE Sponsored Short Term Training Programme on " Mixed Signal and Radio Frequency VLSI Design" on 08 Dec 2020 and 18 Dec 2020, respectively conducted by SGSITS Indore Madhya Pradesh.

3. Emerging Trends in RF and Energy device and Circuits

Delivered an expert talk/lecture in online Faculty Development Program under the MOU with AICTE on “Emerging Trends in RF and Energy device and Circuits” on 23rd Feb 2021 conducted by NIT Meghalaya.

4. Emerging Nanoscale Devices, Circuits and Its Applications

Delivered an expert talk/lecture in online Short-Term Training Program on “Emerging Nanoscale Devices, Circuits and Its Applications” on 12th May 2021 that was organized and sponsored by Department of Electronics and Communication Engineering, Delhi Technological University between May 10-14, 2021.

5. high performance Analog and Mixed signal VLSI System design

Delivered expert talk/lectures in online AICTE training and learning (ATAL) faculty development programme (FDP) on "high performance Analog and Mixed signal VLSI System design" on 16th Dec 2021 (Full day) and 17th Dec 2021 (one lecture) that was organized by IIT Dharwad and sponsored by All India Council for Technical Education (AICTE) between Dec 13-17, 2021.

6. Advances in Signal Processing and VLSI Technologies

Delivered an expert talk/lecture in an online short-term course (STC) on " Advances in Signal Processing and VLSI Technologies" on 6th May 2022 that was organized by NIT Rourkela and sponsored by SERB GoI between 2-6 May 2022.

7. Artificial Intelligence and Its Application in VLSI

Delivered two expert talks/lectures for the faculty development program (FDP) on "Artificial Intelligence and Its Application in VLSI" conducted by the Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Delhi NCR Campus, Ghaziabad, in association with Electronics and ICT Academy of IIT Roorkee from 8th to 12th January 2024 on online mode.

8. India's Techade-Chips for Viksit Bharat

Delivered one expert talk for India's Techade-Chips for Viksit Bharat at Indian Institute of Information Technology (IIIT) Una on 13th March 2024 on online mode.

9. Advancement and Challenges in VLSI Design and Nanoscale Devices

Delivered one expert talk (Date: 29/05/2024) in on a one-week Faculty Development Program on “Advancement and Challenges in VLSI Design and Nanoscale Devices” held between May 27-31, 2024 organized by the Department of Electronics and Communication Engineering, Delhi Technological University, Delhi-110042.

10. Implementing AI-driven Solutions in Engineering and Technology

Delivered one expert talk (Date: 26/09/2024) in Faculty Development Program (FDP) on “Implementing AI-driven Solutions in Engineering and Technology” held between September 23-28, 2024 organized by SCHOOL OF ENGINEERING & TECHNOLOGY IIMT UNIVERSITY, MEERUT.

Outreach Activities

1. Part of InterIIT staff badminton team, tournament held at IIT Guwahati on December 2018.

2. Won first prize in Hindi poem competition held on 24 June 2019 at IIT Ropar.

3. Won first prize in Hindi poem competition held on 19 September 2019 at IIT Ropar.

4. Won second prize in Hindi poem competition held on 18 October 2019 at IIT Ropar.