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Pardeep Duhan

Assistant Professor
319, Department of Electrical Engineering, J C Bose Block, IIT Ropar
pduhan@iitrpr.ac.in
+91-1881-232228
Google Scholar Profile


Introduction

Pardeep Duhan received his Ph.D. in electrical engineering from IIT Bombay, Mumbai, India, in 2017. He was with GlobalFoudries, Singapore, as a Senior Engineer Process Integration and technical staff in Fraunhofer IPMS-CNT, Dresden, Germany. In 2020, he joined the Department of Electrical Engineering at IIT Ropar, Rupnagar, India, as an Assistant Professor. His current research interests include Ferroelectric memory devices, nanoscale device physics, CMOS technology development, and the reliability of semiconductor devices.

Research Highlights

7

Journal Publications

9

Conference Publications

0

Research Projects

0

Patents

0

Awards & Honours

Qualifications
  1. Ph.D. Electrical Engineering Indian Institute of Technology Bombay
  2. M.Tech. Microelectronics Panjab University Chandigarh
  3. M.Sc. Electronic Science Kurukshetra University Kurukshetra
Research Interests
  • Semiconductor Devices
  • Electrical characterization
  • Gate oxide reliability
  • Simulation of Nanodevices
  • Ferroelectric Memory Devices
  • Thin Film Transistors
Brief Research Profile

  1. 1. Prabhat Khedgarkar, Mohit D. Ganeriwala, Pardeep Duhan, "TCAD-based investigation of the origin of 1/f noise in advanced 22 nm FDSOI MOSFETs", Applied Physics Letters (APL), 125,  203506, 2024
  2. 2. Bhairov Kumar Bhowmik, Rohith KM, Pardeep Duhan, Gagan Kumar, "Excitation of high-quality quasi-BIC toroidal mode in a lattice perturbed terahertz metasurface", Applied Physics Letters (APL), 125,  161701, 2024
  3. 3. P. Duhan, T. Ali, P. Khedgarkar, K. Kuhnel, M. Czernohorsky, M. Rudolph, R. Hoffmann, Ayse Sünbül, D.Lehninger, P. Schramm, T. Kämpfe, K. Seidel, "Endurance Study of Silicon-Doped Hafnium Oxide (HSO) and Zirconium-Doped Hafnium Oxide (HZO)-Based FeFET Memory", IEEE Transactions on Electron Devices, 70,  5645-5650, 2023
  4. 4. Pardeep Duhan, V. Ramgopal Rao, Nihar R. Mohapatra, "Effect of device dimensions, layout, and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS Transistors", IEEE Transactions on Device and Materials Reliability, 20,  555-561, 2020
  5. 5. Pardeep Duhan, V. Ramgopal Rao, Nihar R. Mohapatra, "PBTI in HKMG nMOS Transistors - Effect of Width, Layout and other Technological Parameters", IEEE Transactions on Electron Devices, 64,  4018 - 4024, 2017
  6. 6. Satya Siva Naresh, Pardeep Duhan, Nihar R. Mohapatra, "Role of Device Dimensions and Layout on the Analog Performance of Gate First HKMG NMOS Transistors", IEEE Transactions on Electron Devices, 62,  3792 - 3798, 2015
  7. 7. Pardeep Duhan, Mohit Ganeriwala, V. Ramgopal Rao, Nihar R. Mohapatra, "Anomalous Width Dependence of Gate Current in High-K Metal Gate NMOS Transistors", IEEE Electron Device Letters, 36,  739 - 741, 2015

  • 1. Assistant Professor Department of Electrical Engineering Indian Institute of Technology Ropar India (March 2020 - Present)
  • 2. Technical Staff Fraunhofer IPMS-Center Nanoelectronic Technologies Dresden Germany (May 2018 - Feb 2020)
  • 3. Senior Process Integration Engineer GLOBALFOUNDRIES Singapore (May 2017 - March 2018)
  • 4. Visiting Scholar Katholieke Universiteit (KU) /IMEC Leuven Belgium (May 2016 - Aug 2016)
  • 5. DST INSPIRE Fellow Indian Institute of Technology Bombay India (Jan 2012 - Dec 2016)

S. No. Title Funding Agency Role Start Year - End Year Amount (In Lacs) Details

S. No. Title Funding Agency Start Year - End Year Amount (In Lacs) Details

Code Title L-T-P-S-C Type Degree Year Semester