Dr. Pardeep Duhan

Profile Image: 
Name: 
Dr. Pardeep Duhan
Designation: 
Assistant Professor
Department: 
Department of Electrical Engineering
Email: 

pduhan@iitrpr.ac.in

Phone: +91-1881-232228 (Office)

Areas of Research: 
Semiconductor Devices, Electrical characterization, gate oxide reliability, and simulation of Nanodevices, Ferroelectric Memory Devices
Education: 
Ph.D., Electrical Engineering, Indian Institute of Technology Bombay, India, 2017
M.Tech., Microelectronics, Panjab University, Chandigarh, India, 2010
M.Sc., Electronic Science, Kurukshetra University, Kurukshetra, India, 2008
Work Experience: 
Assistant Professor, Department of Electrical Engineering, Indian Institute of Technology Ropar, India (March 2020 - Present)
Technical Staff, Fraunhofer IPMS-Center Nanoelectronic Technologies, Dresden, Germany (May 2018 - Feb 2020)
Senior Process Integration Engineer, GLOBALFOUNDRIES, Singapore (May 2017 - March 2018)
Visiting Scholar, Katholieke Universiteit (KU) /IMEC, Leuven, Belgium (May 2016 - Aug 2016)
DST INSPIRE Fellow, Indian Institute of Technology Bombay, India (Jan 2012 - Dec 2016)
Selected Publications/Patents: 

Journals

1.  P. Duhan, T. Ali, P. Khedgarkar, K. Kuhnel, M. Czernohorsky, M. Rudolph, R. Hoffmann, Ayse Sünbül, D.Lehninger, P. Schramm, T. Kampfe, and K. Seidel, "Endurance Study of Silicon-Doped Hafnium Oxide (HSO) and Zirconium-Doped Hafnium Oxide (HZO)-Based FeFET Memory", IEEE Transactions on Electron Devices, vol. 70, no. 11, pp. 5645-5650, November 2023.

2.  Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra, “Effect of device dimensions, layout, and pre-gate carbon implant on hot carrier induced degradation in HKMG nMOS Transistors”, IEEE Transactions on Device and Materials Reliability, Vol. 20, Issue 3, pp. 555, September 2020.

3.  Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra, “PBTI in HKMG nMOS Transistors - Effect of Width, Layout and other Technological Parameters”, IEEE Transaction on Electron Devices, Vol. 64, Issue 10, pp. 4018, October 2017.

4.  Satya Siva Naresh, Pardeep Duhan and Nihar R. Mohapatra, “Role of Device Dimensions and Layout on the Analog Performance of Gate First HKMG NMOS Transistors”, IEEE Transaction on Electron Devices, Vol. 62, Issue 11, pp. 3792, November 2015.

5.  Pardeep Duhan, Mohit Ganeriwala, V. Ramgopal Rao, and Nihar R. Mohapatra, “Anomalous Width Dependence of Gate Current in High-K Metal Gate NMOS Transistors”, IEEE Electron Device Letters, Vol. 36, Issue 8, pp.739, August 2015.

Conferences

1. Ayse Sünbül, Tarek Ali, Raik Hoffmann, Ricardo Revello, Yannick Raffel, Pardeep Duhan, David Lehninger, Kati Kühnel, Matthias Rudolph, Sebastian Oehler, Philipp Schramm, Malte Czernohorsky, Konrad Seidel, Thomas Kämpfe, and Lukas M. Eng, "Impact of Temperature on Reliability of MFIS HZO-based Ferroelectric Tunnel Junctions", 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2022, pp. P11-1-P11-5.

2.  T. Ali, K. Kühnel, K. Mertens, M. Czernohorsky, M. Rudolph, P. Duhan, D. Lehninger, R. Hoffmann, P. Steinke,  J. Müller, J. Van Houdt, K. Seidel, L. M. Eng, “Effect of Substrate Implant Tuning on the Performance of MFIS Silicon Doped Hafnium Oxide (HSO) FeFET Memory”, IEEE International Memory Workshop (IMW) - 2020, May 2020, Dresden, Germany.

3.  Dang Khoa, Quang Huy Le, Pardeep Duhan, Defu Wang, Thomas Kämpfe, and Matthias Rudolph, “Analysis of hot-carrier degradation in 22nm FDSOI transistors using RF-small signal characteristics”, German Microwave Conference (GeMiC) - 2020, March 2020, Cottbus, Germany.

4.  J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta, “Statistical model of the NBTI-induced threshold voltage, subthreshold swing, and transconductance degradations in advanced p-FinFETs”, International Electron Devices Meeting (IEDM) - 2016, December 2016, San Francisco, CA, USA.

5.  Pardeep Duhan, V. Ramgopal Rao and Nihar R. Mohapatra, “Width and Layout dependence of HC and PBTI induced degradation in HKMG NMOS Transistors”, International Reliability Physics Symposium (IRPS) - 2016, April 2016, Pasadena, CA, USA.

6.  Pardeep Duhan, Nihar R. Mohapatra and Sharad Kumar Jain, “Width Dependence of HCI and PBTI in HKMG NMOS Transistors”, Proceedings of ICMAT and IUMRS, June 2015, Singapore.

7.  Nihar R. Mohapatra, Satya Siva Naresh and Pardeep Duhan, “Analog Performance of Gate-First HKMG NMOS Transistors-Role of Device Dimensions and Layout”, Proceedings of International Symposium in VLSI Technology, Systems and Applications (VLSI-TSA), April 2015, Taiwan.

8.  Satya Siva Naresh, Nihar R. Mohapatra and Pardeep Duhan, “Effects of HfO2 and Lanthanum capping Layer Thickness on Narrow Width Behavior of Gate First High-K Metal Gate NMOS Transistors”, Proceedings of International Conference on Solid State Devices and Materials (SSDM 2013), September 2013, Fukuoka, Japan.

9.  V.K.Khanna, P. Duhan, “Modeling the Current-Voltage characteristics & Temporal Drift in Threshold Voltage of ISFET for pH Measurements”, 2nd ISSS National Conference on MEMS, Microsensors, Smart Materials, Structures and Systems, November 2007, CEERI Pilani, Rajasthan, India.